ARCHITECTURE OF THE SPS-1000 SUPERFAST FFT PROCESSOR.

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作者：
Fisher, Joseph R.
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Conference Record - Electro | 1980年
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Computer architecture - MATHEMATICAL TRANSFORMATIONS - Fast Fourier Transforms;
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摘要：
A new FFT Processor called the SPS-1000 was developed which is similar to the pipelined FFT Processor architecture, but permitting parallel as well as cascaded processing elements. Using a set of standard building-block modules, including a butterfly module, storage module and several supporting module types, FFT processors and convolvers with throughput rates in excess of 13 MHz can be configured. SPS-1000 modules are byte sliced so that SPS-1000 systems with arithmetic word lengths of 8, 16, 24 and 32 bits can be provided to suit the dynamic range requirements of the application.
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