Transport triggered architecture processor for mixed-radix FFT

Transport triggered architecture (TTA) offers a cost-effective trade-off between the energy-efficiency and performance of an ASIC implementation and the flexibility provided by a software implementation on a programmable processor. In this paper, a programmable TTA processor is described, which is tailored for computing mixed-radix fast Fourier transform (FFT). Several approaches has been exploited to reduce the power consumption, e.g., special function units for complex-valued arithmetic and address computation, clock gating, and instruction compression. The paper describes an FFT implementation supporting power-of-two FFTs with the aid of mixed-radix algorithm based on radix-4 and radix-2 computations. The developed processor is programmable but shows energy-efficiency comparable to fixed-function ASIC implementations.