A 400 MFLOPS FFT PROCESSOR VLSI ARCHITECTURE

被引：0
|
作者：
MIYANAGA, H
YAMAUCHI, H
机构：
来源：
IEICE TRANSACTIONS ON COMMUNICATIONS ELECTRONICS INFORMATION AND SYSTEMS | 1991年 / 74卷 / 11期
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We propose a single-chip 400-MFLOPS 2-D FFT processor VLSI architecture. This processor integrates 380,000 transistors in an area of 11.58 x 11.58 mm2 using 0.8-mu-m CMOS technology with a typical machine cycle time of 25 ns, and executes 2n x 2n point 2-D FFT in real time, e.g., 256 x 256 point FFT is executed in 14 ms. This excellent performance in terms of both speed and dynamic range makes the real-time processing practical for video as well as speech processing.
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页码：3845 / 3851
页数：7
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