A 45NS 16X16 CMOS MULTIPLIER

被引:0
|
作者
KAJI, Y
SUGIYAMA, N
KITAMURA, Y
OHYA, S
KIKUCHI, M
机构
来源
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:84 / 85
页数:2
相关论文
共 50 条
  • [1] A 3.8NS CMOS 16X16 MULTIPLIER USING COMPLEMENTARY PASS TRANSISTOR LOGIC
    YANO, K
    YAMANAKA, T
    NISHIDA, T
    SAITOH, M
    SHIMOHIGASHI, K
    SHIMIZU, A
    [J]. PROCEEDINGS OF THE IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1989, : 243 - 246
  • [2] A SUB-10-NS 16X16 MULTIPLIER USING 0.6-MU-M CMOS TECHNOLOGY
    OOWAKI, Y
    NUMATA, K
    TSUCHIYA, K
    TSUDA, K
    TAKATO, H
    TAKENOUCHI, N
    NITAYAMA, A
    KOBAYASHI, T
    CHIBA, M
    WATANABE, S
    OHUCHI, K
    HOJO, A
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) : 762 - 767
  • [3] A NMOS LSI 16X16 MULTIPLIER
    WITTMER, NC
    MICHEJDA, JA
    GANNETT, JW
    BECHTOLD, PF
    TAYLOR, GW
    LIFSHITZ, N
    DENNIS, DC
    BAYRUNS, RJ
    [J]. ISSCC DIGEST OF TECHNICAL PAPERS, 1983, 26 : 32 - 33
  • [4] A GAAS 16X16 BIT PARALLEL MULTIPLIER
    NAKAYAMA, Y
    SUYAMA, K
    SHIMIZU, H
    YOKOYAMA, N
    OHNISHI, H
    SHIBATOMI, A
    ISHIKAWA, H
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) : 599 - 603
  • [5] Design and Implementation of 16x16 Modified Booth Multiplier
    Manjunath
    Harikiran, Venama
    Manikanta, Kopparapu
    Sivanantham, S.
    Sivasankaran, K.
    [J]. PROCEEDINGS OF 2015 ONLINE INTERNATIONAL CONFERENCE ON GREEN ENGINEERING AND TECHNOLOGIES (IC-GET), 2015,
  • [6] A MULTICHIP PACKAGED GAAS 16X16 PARALLEL MULTIPLIER
    SEKIGUCHI, T
    SAWADA, S
    HIROSE, T
    NISHIGUCHI, M
    SHIGA, N
    HAYASHI, H
    [J]. IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1992, 15 (04): : 444 - 450
  • [7] 45ns的16位乘法器
    宁众
    [J]. 微纳电子技术, 1985, (02) : 39 - 39
  • [8] A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device
    Kim, Yong-Hyun
    Choi, Jong-Moon
    Woo, Je-Joong
    Park, Eun-Je
    Kim, Sang-Won
    Kwon, Kee-Won
    [J]. 2019 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC), 2019, : 263 - 266
  • [9] Design and Optimization of 16x16 Bit Multiplier Using Vedic Mathematics
    Gadakh, Sheetal N.
    Khade, Amitkumar
    [J]. 2016 INTERNATIONAL CONFERENCE ON AUTOMATIC CONTROL AND DYNAMIC OPTIMIZATION TECHNIQUES (ICACDOT), 2016, : 460 - 464
  • [10] 16X16 Fast Signed Multiplier Using Booth and Vedic Architecture
    Shing, L. Z.
    Hussin, R.
    Kamarudin, A.
    Mohyar, S. N.
    Taking, S.
    Aziz, M. H. A.
    Ahmad, N.
    [J]. 4TH ELECTRONIC AND GREEN MATERIALS INTERNATIONAL CONFERENCE 2018 (EGM 2018), 2018, 2045