共 19 条
- [3] A 3.8NS CMOS 16X16 MULTIPLIER USING COMPLEMENTARY PASS TRANSISTOR LOGIC [J]. PROCEEDINGS OF THE IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1989, : 243 - 246
- [4] Design and Optimization of 16x16 Bit Multiplier Using Vedic Mathematics [J]. 2016 INTERNATIONAL CONFERENCE ON AUTOMATIC CONTROL AND DYNAMIC OPTIMIZATION TECHNIQUES (ICACDOT), 2016, : 460 - 464
- [5] 16X16 Fast Signed Multiplier Using Booth and Vedic Architecture [J]. 4TH ELECTRONIC AND GREEN MATERIALS INTERNATIONAL CONFERENCE 2018 (EGM 2018), 2018, 2045
- [9] The design of 16x16 wave pipelined multiplier using fan-in equalization technique [J]. 40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 1998, : 336 - 339
- [10] A novel CMOS compatible stacked floating gate device using TiN as a control gate [J]. 1997 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1997, : 61 - 62