A SUB-10-NS 16X16 MULTIPLIER USING 0.6-MU-M CMOS TECHNOLOGY

被引:8
|
作者
OOWAKI, Y
NUMATA, K
TSUCHIYA, K
TSUDA, K
TAKATO, H
TAKENOUCHI, N
NITAYAMA, A
KOBAYASHI, T
CHIBA, M
WATANABE, S
OHUCHI, K
HOJO, A
机构
[1] Toshiba Corp, Kawasaki, Jpn, Toshiba Corp, Kawasaki, Jpn
关键词
Compendex;
D O I
10.1109/JSSC.1987.1052811
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
15
引用
收藏
页码:762 / 767
页数:6
相关论文
共 48 条
  • [1] A 45NS 16X16 CMOS MULTIPLIER
    KAJI, Y
    SUGIYAMA, N
    KITAMURA, Y
    OHYA, S
    KIKUCHI, M
    [J]. ISSCC DIGEST OF TECHNICAL PAPERS, 1984, 27 : 84 - 85
  • [2] A 3.8NS CMOS 16X16 MULTIPLIER USING COMPLEMENTARY PASS TRANSISTOR LOGIC
    YANO, K
    YAMANAKA, T
    NISHIDA, T
    SAITOH, M
    SHIMOHIGASHI, K
    SHIMIZU, A
    [J]. PROCEEDINGS OF THE IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1989, : 243 - 246
  • [3] 0.6-MU-M CMOS TECHNOLOGY USING DESIRE PROCESS
    VINET, F
    CHEVALLIER, M
    GUIBERT, JC
    PIERRAT, C
    [J]. ADVANCES IN RESIST TECHNOLOGY AND PROCESSING VI, 1989, 1086 : 433 - 443
  • [4] A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device
    Kim, Yong-Hyun
    Choi, Jong-Moon
    Woo, Je-Joong
    Park, Eun-Je
    Kim, Sang-Won
    Kwon, Kee-Won
    [J]. 2019 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC), 2019, : 263 - 266
  • [5] Design and Optimization of 16x16 Bit Multiplier Using Vedic Mathematics
    Gadakh, Sheetal N.
    Khade, Amitkumar
    [J]. 2016 INTERNATIONAL CONFERENCE ON AUTOMATIC CONTROL AND DYNAMIC OPTIMIZATION TECHNIQUES (ICACDOT), 2016, : 460 - 464
  • [6] 16X16 Fast Signed Multiplier Using Booth and Vedic Architecture
    Shing, L. Z.
    Hussin, R.
    Kamarudin, A.
    Mohyar, S. N.
    Taking, S.
    Aziz, M. H. A.
    Ahmad, N.
    [J]. 4TH ELECTRONIC AND GREEN MATERIALS INTERNATIONAL CONFERENCE 2018 (EGM 2018), 2018, 2045
  • [7] A HIGH-SPEED 0.6-MU-M 16K CMOS GATE ARRAY ON A THIN SIMOX FILM
    YAMAGUCHI, Y
    ISHIBASHI, A
    SHIMIZU, M
    NISHIMURA, T
    TSUKAMOTO, K
    HORIE, K
    AKASAKA, Y
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (01) : 179 - 186
  • [8] VLSI implementation of a 200-MHz 16x16 left-to-right carry-free multiplier in 0.35 mu m CMOS technology for next-generation DSPs
    Kolagotla, RK
    Srinivas, HR
    Burns, GF
    [J]. PROCEEDINGS OF THE IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1997, : 469 - 472
  • [9] VHDL implementation of 16x16 multiplier using pipelined 16x8 modified Radix-4 booth multiplier
    Tawfeek, Radwa M.
    Elmenyawi, Marwa A.
    [J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 2023, 110 (06) : 971 - 985
  • [10] A 6.75-NS 16X16-BIT MULTIPLIER IN SINGLE-LEVEL-METAL CMOS TECHNOLOGY
    SHARMA, R
    LOPEZ, AD
    MICHEJDA, JA
    HILLENIUS, SJ
    ANDREWS, JM
    STUDWELL, AJ
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (04) : 922 - 927