A MULTICHIP PACKAGED GAAS 16X16 PARALLEL MULTIPLIER

被引：0
|
作者：
SEKIGUCHI, T
SAWADA, S
HIROSE, T
NISHIGUCHI, M
SHIGA, N
HAYASHI, H
机构：
[1] Optoelectronics Laboratories, Sumitomo Electric Industries Ltd., Sakae-ku
来源：
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY | 1992年 / 15卷 / 04期
关键词：
D O I：
10.1109/33.159872
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
A GaAs 16 x 16 b parallel multiplier utilizing multichip packaging technology is demonstrated. This multichip approach is undertaken in an effort to realize GaAs ULSI's with high yield and reliability, using multiple smaller scale integrated circuits. The device is composed of four GaAs 8 x 8 expandable parallel multipliers and a multichip package (MCP). The developed 8 x 8 b multipliers consist of 1097 E/D DCFL gates each and have a 3.4 ns multiplication time. The developed MCP is composed of five layers of alumina ceramic which include 50-OMEGA strip lines. The multiplication time of this 16 x 16 b multichip multiplier is 7.6 ns, and the total production yield is 70%.
引用
收藏
页码：444 / 450
页数：7
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