A MULTICHIP PACKAGED GAAS 16X16 PARALLEL MULTIPLIER

被引：0
|
作者：
SEKIGUCHI, T
SAWADA, S
HIROSE, T
NISHIGUCHI, M
SHIGA, N
HAYASHI, H
机构：
[1] Optoelectronics Laboratories, Sumitomo Electric Industries Ltd., Sakae-ku
来源：
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY | 1992年 / 15卷 / 04期
关键词：
D O I：
10.1109/33.159872
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
A GaAs 16 x 16 b parallel multiplier utilizing multichip packaging technology is demonstrated. This multichip approach is undertaken in an effort to realize GaAs ULSI's with high yield and reliability, using multiple smaller scale integrated circuits. The device is composed of four GaAs 8 x 8 expandable parallel multipliers and a multichip package (MCP). The developed 8 x 8 b multipliers consist of 1097 E/D DCFL gates each and have a 3.4 ns multiplication time. The developed MCP is composed of five layers of alumina ceramic which include 50-OMEGA strip lines. The multiplication time of this 16 x 16 b multichip multiplier is 7.6 ns, and the total production yield is 70%.
引用
收藏
页码：444 / 450
页数：7
相关论文
共 50 条
  • [21] Characteristics of 16x16 micro optical switch
    Choi, H
    Yoon, Y
    Kim, JH
    Kim, YS
    [J]. 2002 IEEE/LEOS INTERNATIONAL CONFERENCE ON OPTICAL MEMS, CONFERENCE DIGEST, 2002, : 109 - 110
  • [22] 8X8 MULTIPLIER AND 8-BIT MU-P PERFORM 16X16 BIT MULTIPLICATION
    MOR, S
    [J]. EDN MAGAZINE-ELECTRICAL DESIGN NEWS, 1979, 24 (20): : 147 - 152
  • [23] VLSI IMPLEMENTATION OF A 16X16 DISCRETE COSINE TRANSFORM
    SUN, MT
    CHEN, TC
    GOTTLIEB, AM
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (04): : 610 - 617
  • [24] HIGH-SPEED GaAs 16 multiplied by 16-BIT PARALLEL MULTIPLIER.
    Nakayama, Yoshiro
    Suyama, Katsuhiko
    Shimizu, Haruo
    [J]. Fujitsu Scientific and Technical Journal, 1983, 19 (04): : 417 - 429
  • [25] High Speed 16x16 bit Booth Multiplier Based on Novel 4-2 Compressor Structure
    Rahnamaei, Ali
    Fatin, Gholamreza Zare
    [J]. 2018 1ST INTERNATIONAL CONFERENCE ON ADVANCED RESEARCH IN ENGINEERING SCIENCES (ARES), 2018,
  • [26] A SUB-10-NS 16X16 MULTIPLIER USING 0.6-MU-M CMOS TECHNOLOGY
    OOWAKI, Y
    NUMATA, K
    TSUCHIYA, K
    TSUDA, K
    TAKATO, H
    TAKENOUCHI, N
    NITAYAMA, A
    KOBAYASHI, T
    CHIBA, M
    WATANABE, S
    OHUCHI, K
    HOJO, A
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) : 762 - 767
  • [27] A 16X16 CROSSPOINT SWITCH FOR TERNARY ENCODED SIGNALS
    JAYAKUMAR, A
    YOUNG, KC
    [J]. IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 1988, 6 (03) : 566 - 571
  • [28] 16x16 Two-dimensional optoelectronic integrated receiver array for highly parallel interprocessor networks
    Yano, H
    Sawada, S
    Doguchi, K
    Kato, T
    Sasaki, G
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 1997, E80C (05) : 689 - 694
  • [29] Polymeric 16x16 digital optical switch matrix
    Rabbering, FLW
    van Nunen, JFP
    Eldada, L
    [J]. ECOC'01: 27TH EUROPEAN CONFERENCE ON OPTICAL COMMUNICATION, VOLS 1-6, 2001, : A78 - A79
  • [30] A Paralleled Greedy LLL Algorithm for 16x16 MIMO Detection
    Chen, Lirui
    Wang, Yu
    Xing, Zuocheng
    Qiu, Shikai
    Wang, Qinglin
    Zhang, Yang
    [J]. 2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,
12345