共 50 条
- [2] 16X16 Fast Signed Multiplier Using Booth and Vedic Architecture [J]. 4TH ELECTRONIC AND GREEN MATERIALS INTERNATIONAL CONFERENCE 2018 (EGM 2018), 2018, 2045
- [5] A GAAS 16X16 BIT PARALLEL MULTIPLIER [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) : 599 - 603
- [6] Design and Optimization of 16x16 Bit Multiplier Using Vedic Mathematics [J]. 2016 INTERNATIONAL CONFERENCE ON AUTOMATIC CONTROL AND DYNAMIC OPTIMIZATION TECHNIQUES (ICACDOT), 2016, : 460 - 464
- [7] A High-Speed, Hierarchical 16x16 Array of Array Multiplier Design [J]. 2009 INTERNATIONAL CONFERENCE ON MULTIMEDIA, SIGNAL PROCESSING AND COMMUNICATION TECHNOLOGIES, 2009, : 161 - +
- [8] A MULTICHIP PACKAGED GAAS 16X16 PARALLEL MULTIPLIER [J]. IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1992, 15 (04): : 444 - 450
- [10] High Speed 16x16 bit Booth Multiplier Based on Novel 4-2 Compressor Structure [J]. 2018 1ST INTERNATIONAL CONFERENCE ON ADVANCED RESEARCH IN ENGINEERING SCIENCES (ARES), 2018,