VLSI implementation of high speed multiplier architecture using VHBCSE algorithm for DSP applications

In this paper, the synchronous pipelined architecture of the Vertical Horizontal Binary Common Subexpression Elimination (VHBCSE) based FIR filter for DSP applications, namely multi-standard wireless communication and Software Defined Radio (SDR), was realised. In VLSI design, high speed and low power construction were focused on achieving the minimum area. Here we can improve the throughput of the design. Traditionally, the pipelined technique provides the solution for better throughput of any design. In this proposed synchronous pipelined architecture design, the improvement in speed was obtained while reducing critical path delay by adding additional registers between the combinations of blocks. The VHBCSE architecture efficiency in area power product (APP) as well as speed of the design was improved by 28% and 40% from the existing VHBCSE multiplier.