Implementation of Low Voltage MOSFET and Power LDMOS on InGaAs

In this paper, a new low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) have been proposed with concept of integration based on trench technology on InGaAs material. Junction isolation technique is used for the implementation of a low voltage MOSFET and a high power dual gate MOSFET in same InGaAs epitaxial layer side by side. The HV DG MOSFET consists of dual gate that are placed in drift region under the oxide-filled trenches. The proposed structure minimize on-resistance (Ron) along with increased breakdown voltage (Vbr) due to enhanced RESURF effect, the creation of dual channels, and due to folding technique of drift region in vertical direction. In the HV DG MOSFET, the drain current (ID) increases leading to enhanced transconductance (gm) by simultaneous conduction of channels with improved maximum oscillation frequency (fmax) and cut-off frequency (ft). On the other side, the low voltage MOSFET consists of a gate placed in a centre of the structure within an oxide trench to create two n-channels in the p-base. The two channels are conducting in parallel and give substantial enhancement in peak gm, ID, fmax and ft with more control over the short channel parameters. The design and performance analysis of low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) are carried out on 2-D ATLAS device simulator.