Power switch implementation for low voltage digital circuits

This letter presents a novel power switch structure using only low threshold voltage MOSFETs to extend the power switch to ultra-low voltage region. The proposed structure deploys series-connected low-Vth footers with two virtual ground ports and selectively chooses the logic cells for connecting to each virtual ground port according to the delay criticality. Moreover, additional circuitries are designed to reduce not only sub-threshold leakage current, but also gate-tunneling leakage and to reduce wake-up time and wake-up fluctuation compared to the conventional power switch. The total power switch size of the proposed power switch structure including the additional circuits is less than the conventional one. The simulation results show that the proposed power gating structure has advantage of low leakage power, small footer size, and low wake-up time, but high-performance, low wake-up fluctuation, wake-up power for inverter chains and ISCAS85 benchmark circuits at 1.1V and 0.6V VDD which are designed using 45nm CMOS technology.