A SURVEY OF LOW-VOLTAGE LOW-POWER TECHNIQUES AND CHALLENGES FOR CMOS DIGITAL CIRCUITS

被引：10
|
作者：
Hung, Yu-Cherng [1 ]
Shieh, Shao-Hui [1 ]
Tung, Chiou-Kou [1 ]
机构：
[1] Natl Chin Yi Univ Technol, Dept Elect Engn, Taichung Cty 411, Taiwan
来源：
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2011年 / 20卷 / 01期
关键词：
Low voltage; low power; LVLP; BACK-GATE; PERFORMANCE; LEAKAGE; DESIGN; SCHEME; OPTIMIZATION; COMPARATOR; REDUCTION; ALGORITHM;
D O I：
10.1142/S0218126611007104
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivations and challenges of CMOS low-voltage low-power circuit are addressed. Various design methodologies are surveyed and summarized in whole. The paper attempts to quickly give readers a full-view conception in low-voltage low-power CMOS system design.
引用
收藏
页码：89 / 105
页数：17
相关论文
共 50 条
  • [1] LOW-VOLTAGE, LOW-POWER BICMOS DIGITAL CIRCUITS
    ROFAIL, SS
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (05) : 572 - 579
  • [2] Low-power and low-voltage CMOS digital design
    Piguet, C
    MICROELECTRONIC ENGINEERING, 1997, 39 (1-4) : 179 - 208
  • [3] Low-power and low-voltage CMOS digital design
    CSEM Cent Suisse d'Electronique et, de Microtechnique SA, Neuchatel, Switzerland
    Microelectron Eng, 1-4 (179-208):
  • [4] CMOS/SOI technologies for low-power and low-voltage circuits
    Pelloie, JL
    Raynaud, C
    Faynot, O
    Grouillet, A
    de Pontcharra, JD
    MICROELECTRONIC ENGINEERING, 1999, 48 (1-4) : 327 - 334
  • [5] A Survey of Low-Voltage Low-Power Technique and Challenge for CMOS Signal Processing Circuits
    Hung, Yu-Cherng
    Chen, Jian-Cheng
    Shieh, Shao-Hui
    Tung, Chiou-Kou
    PROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009), 2009, : 236 - 239
  • [6] Process compensation techniques for low-voltage CMOS digital circuits
    Graduate School of Information Science and Technology, Hokkaido University, kita 14, nishi 9, kita-ku, Sapporo 060-0814, Japan
    不详
    Kyokai Joho Imeji Zasshi, 2009, 11 (1667-1670):
  • [7] Low-Voltage Low-Power CMOS Design
    Dokic, Branko L.
    Pesic-Brdanin, Tatjana
    Cavka, Drago
    2016 INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (INDEL), 2016,
  • [8] Low-voltage, low-power basic circuits
    Baschirotto, A
    D'Amico, S
    Malcovati, P
    ANALOG CIRCUIT DESIGN: RF CIRCUITS: WIDE BAND, FRONT-ENDS,DAC'S, DESIGN METHODOLOGY AND VERIFICATION FOR RF AND MIXED-SIGNAL SYSTEMS, LOW POWER AND LOW VOLTAGE, 2006, : 295 - +
  • [9] Low-voltage low-power improved linearity CMOS active resistor circuits
    Anca Manolescu
    Cosmin Popa
    Analog Integrated Circuits and Signal Processing, 2010, 62 : 373 - 387
  • [10] Low-voltage low-power improved linearity CMOS active resistor circuits
    Manolescu, Anca
    Popa, Cosmin
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2010, 62 (03) : 373 - 387
12345