Wafer-level bonding/stacking technology for 3D integration

被引：159
|
作者：
Ko, Cheng-Ta [1 ]
Chen, Kuan-Neng [1 ]
机构：
[1] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 300, Taiwan
来源：
MICROELECTRONICS RELIABILITY | 2010年 / 50卷 / 04期
关键词：
SILICON;
D O I：
10.1016/j.microrel.2009.09.015
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Enhanced transmission speeds, lower power consumption, better performance, and smaller form factors are reported as advantages in many devices and applications when using 3D integration. One core technique for performing 3D interconnection is stacked bonding. In this paper, wafer-level bonding technologies are reviewed and described in detail, including bonding materials and bonding conditions. The corresponding 3D integration technologies and platforms developed world-wide are also organized and addressed. (C) 2009 Elsevier Ltd. All rights reserved.
引用
收藏
页码：481 / 488
页数：8
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