Dielectric glue wafer bonding and bonded wafer thinning for wafer-level 3D integration

被引：0
|
作者：
Lu, JQ [1 ]
Kwon, Y [1 ]
Jindal, A [1 ]
McMahon, JJ [1 ]
Cale, TS [1 ]
Gutmann, RJ [1 ]
机构：
[1] Rensselaer Polytech Inst, Rensselaer Interconnect Gigascale Integrat, Focus Ctr New York, Troy, NY 12180 USA
来源：
SEMICONDUCTOR WAFER BONDING VII: SCIENCE, TECHNOLOGY, AND APPLICATIONS, PROCEEDINGS | 2003年 / 2003卷 / 19期
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Baseline processes established for 200 mm wafer bonding (using polymers as dielectric bonding glue) and bonded wafer thinning (using backgrinding, polishing, and etching) are presented, which are two critical processes in our approach to monolithic wafer-level 3D ICs. Four-point bending technique is used to quantify the bonding strength, identify the weak interface, and study their dependence on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). Mechanical and electrical properties of processed wafers with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding and thinning processes for 3D ICs.
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页码：76 / 86
页数：11
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