3D Integration by Wafer-Level Aligned Wafer Bonding

被引：0
|
作者：
Dragoi, V. [1 ]
Burggraf, J. [1 ]
Kurz, F. [1 ]
Rebhan, B. [1 ]
机构：
[1] EV Grp, DI E Thallner 1,4782 St, Florian Inn, Austria
来源：
2015 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS) | 2015年
关键词：
wafer bonding; low temperature; high alignment accuracy; hybrid bonding; thin Si wafers stacking; STACKING;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Wafer bonding is an attractive technology enabling manufacturing of complex wafer-level 3D architectures. The continuous demand for device size shrinking and performance improvement pushed for the development of new manufacturing technologies. This work reviews the main challenging raised for the wafer bonding processes and presents new developments in the aligned wafer bonding processes.
引用
收藏
页码：185 / 188
页数：4
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