Wafer-level 3D integration technology

被引：135
|
作者：
Koester, S. J. [1 ]
Young, A. M. [1 ]
Yu, R. R. [1 ]
Purushothaman, S. [1 ]
Chen, K. -N. [1 ]
La Tulipe, D. C., Jr. [1 ]
Rana, N. [1 ]
Shi, L. [1 ]
Wordeman, M. R. [1 ]
Sprogis, E. J. [2 ]
机构：
[1] IBM Corp, Div Res, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
[2] IBM Corp, Syst & Technol Grp, Essex Jct, VT 05452 USA
来源：
IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 2008年 / 52卷 / 06期
关键词：
D O I：
10.1147/JRD.2008.5388565
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.
引用
收藏
页码：583 / 597
页数：15
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