Wafer-level 3D integration technology

被引：135
|
作者：
Koester, S. J. [1 ]
Young, A. M. [1 ]
Yu, R. R. [1 ]
Purushothaman, S. [1 ]
Chen, K. -N. [1 ]
La Tulipe, D. C., Jr. [1 ]
Rana, N. [1 ]
Shi, L. [1 ]
Wordeman, M. R. [1 ]
Sprogis, E. J. [2 ]
机构：
[1] IBM Corp, Div Res, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA
[2] IBM Corp, Syst & Technol Grp, Essex Jct, VT 05452 USA
来源：
IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 2008年 / 52卷 / 06期
关键词：
D O I：
10.1147/JRD.2008.5388565
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.
引用
收藏
页码：583 / 597
页数：15
相关论文
共 50 条
  • [21] Wafer-level 3D integration with 5 micron interconnect pitch for infrared imaging applications
    Lueck, Matthew
    Lannon, John, Jr.
    Gregory, Chris
    Malta, Dean
    Huffman, A.
    Temple, Dorota S.
    [J]. IMAGE SENSING TECHNOLOGIES: MATERIALS, DEVICES, SYSTEMS, AND APPLICATIONS, 2014, 9100
  • [22] High Precision Low Temperature Direct Wafer Bonding Technology for Wafer-Level 3D ICs Manufacturing
    Kurz, F.
    Plach, T.
    Suess, J.
    Wagenleitner, T.
    Zinner, D.
    Rebhan, B.
    Dragoi, V.
    [J]. SEMICONDUCTOR WAFER BONDING: SCIENCE, TECHNOLOGY AND APPLICATIONS 14, 2016, 75 (09): : 345 - 353
  • [23] Polymer for Wafer-level Hybrid Bonding and Its Adhesion to Passivation Layer in 3D Integration
    Lu, Cheng-Hsien
    Kho, Yi-Tung
    Cheng, Chuan-An
    Huang, Yen-Jun
    Chen, Kuan-Neng
    [J]. 2017 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING (ICEP), 2017, : 519 - 521
  • [24] Wafer-level 3D interconnects via Cu bonding
    Morrow, P
    Kobrinsky, MJ
    Ramanathan, S
    Park, CM
    Harmes, M
    Ramachandrarao, V
    Park, HM
    Kloster, G
    List, S
    Kim, S
    [J]. ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004), 2004, : 125 - 130
  • [25] A Study on Wafer-Level 3D Integration Including Wafer Bonding using Low-k Polymeric Adhesive
    Kwon, Yongchai
    Seok, Jongwon
    Lu, Jian-Qiang
    Cale, Timothy
    Gutmann, Ronald
    [J]. KOREAN CHEMICAL ENGINEERING RESEARCH, 2007, 45 (05): : 466 - 472
  • [26] 3D EMBEDDED WAFER-LEVEL PACKAGING TECHNOLOGY DEVELOPMENT FOR SMART CARD SIP APPLICATION
    Pares, G.
    Bouvier, C.
    Saadaoui, M.
    Mazuir, J.
    Noiray, J.
    Martinschitz, K.
    Planchais, A.
    Simon, G.
    [J]. PROCEEDINGS OF THE 2012 IEEE 14TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, 2012, : 304 - 310
  • [27] Low Cost Wafer-Level 3-D Integration without TSV
    Toepper, Michael
    Baumgartner, Tobias
    Klein, Matthias
    Fritzsch, Thomas
    Roeder, Julia
    Lutz, Mario
    von Suchodoletz, Maria
    Oppermann, Hermann
    Reichl, Herbert
    [J]. 2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 339 - 344
  • [28] Wafer-level 3D manufacturing issues for streaming video processors
    Zeng, AY
    Lu, JQ
    Gutmann, RJ
    Rose, K
    [J]. 2004 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP: ADVANCING THE SCIENCE AND TECHNOLOGY OF SEMICONDUCTOR MANUFACTURING EXCELLENCE, 2004, : 247 - 251
  • [29] Fine keyed alignment and bonding for wafer-level 3D ICs
    Lee, Sang Hwui
    Niklaus, Frank
    McMahon, J. Jay
    Yu, Jian
    Kumar, Ravi J.
    Li, Hui-Feng
    Gutmann, Ronald J.
    Cale, Timothy S.
    Lu, J. -Q.
    [J]. MATERIALS, TECHNOLOGY AND RELIABILITY OF LOW-K DIELECTRICS AND COPPER INTERCONNECTS, 2006, 914 : 433 - +
  • [30] Demonstration of a 3D Embedded Wafer-Level SIP for Smartcard Application
    Pares, G.
    Bouvier, C.
    Castagne, L.
    Saadaoui, M.
    Mazuir, J.
    Noiray, J.
    Martinschitz, K.
    Mercier, L.
    Planchais, A.
    Simon, G.
    [J]. 2013 EUROPEAN MICROELECTRONICS PACKAGING CONFERENCE (EMPC), 2013,
12345