Building blocks for wafer-level 3D integration

被引:0
|
作者
Sadaka, Mariam [1 ]
Di Cioccio, Lea [2 ]
机构
[1] Soitec USA Inc, Austin, TX 78746 USA
[2] CEA, DRT LETI, F-38054 Grenoble, France
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The microelectronic industry has at a crossroads. There is the challenge of continued Moore's Law scaling and the ever-growing consumer demand for smaller, faster with extended and new functionalities. 3D integration is a promising and fast-growing field that addresses the convergence of Moore's Law and more than Moore. 3D integration offers a path for high performance, higher density, higher functionality, small form factor, and potential cost reduction. Through this emerging field, new and improved technologies and integration schemes will be necessary to meet the associated manufacturing challenges. With the possibility of addressing different process flows, this paper describes 3D building blocks, including stacking technology as well as a low temperature layer transfer technology and a metal-to-metal bonding technique.
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页码:20 / +
页数:4
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