The design and implementation of DCT/IDCT chip with novel architecture

被引：0

作者：

Cheng, KH ^{[1
]}

Huang, CS ^{[1
]}

Lin, CP ^{[1
]}

机构：

[1] Tamkang Univ, Dept Elect Engn, Taipei, Taiwan

来源：

ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In the paper, an efficient VLSI architecture for a 8x 8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm [1]. For computing 2-D DCT/IDCT. the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 mu m standard cell library and 1P3M CMOS technology, and it can be operate up to 100MHz.

引用

页码：741 / 744

页数：4

共 50 条

[41] High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip
G. A. Ruiz
J. A. Michell
A. Burón
Journal of VLSI signal processing systems for signal, image and video technology, 2006, 45 : 161 - 175
[42] DATA MAPPING SCHEME AND IMPLEMENTATION FOR HIGH-THROUGHPUT DCT/IDCT TRANSPOSE MEMORY
Xie, Zheng
Lu, Yanheng
Fan, Yibo
Zeng, Xiaoyang
2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
[43] An efficient unified framework for implementation of a prime-length DCT/IDCT with high throughput
Chiper, Doru-Morin
Swamy, M. N. S.
Ahmad, M. Omair
IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2007, 55 (06) : 2925 - 2936
[44] High throughput parallel-pipeline 2-D DCT/IDCT processor chip
Ruiz, G. A.
Michell, J. A.
Buron, A.
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2006, 45 (03): : 161 - 175
[45] Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular Automata
Bahar, Ali Newaz
Wahid, Khan A.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (12) : 2530 - 2539
[46] Design and Implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore Architecture
Pourabed, Mohammad Ali
Nouri, Sajjad
Nurmi, Jari
2018 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), 2018,
[47] Low power design of DCT and IDCT for low bit rate video codecs
August, NJ
Ha, DS
IEEE TRANSACTIONS ON MULTIMEDIA, 2004, 6 (03) : 414 - 422
[48] Effective Hardware Accelerator for 2D DCT/IDCT Using Improved Loeffler Architecture
Zhou, Zhiwei
Pan, Zhongliang
IEEE ACCESS, 2022, 10 : 11011 - 11020
[49] A Four Quadrants Parallel-Recursive 2-D DCT/IDCT VLSI Architecture
Purwita, Ardimas Andi
Adiono, Trio
PROCEEDINGS OF THE 2012 FIFTH INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET 2012), 2012, : 233 - 238
[50] Hardware Implementation of Low Power, High Speed DCT/IDCT Based Digital Image Watermarking
Megalingam, Rajesh Kannan
Krishnan, Venkat B.
Sarma, Vineeth V.
Mithun, M.
Srikumar, Rahul
PROCEEDINGS OF THE 2009 INTERNATIONAL CONFERENCE ON COMPUTER TECHNOLOGY AND DEVELOPMENT, VOL 1, 2009, : 535 - 539

← 1 2 3 4 5 →