The design and implementation of DCT/IDCT chip with novel architecture

被引：0

作者：

Cheng, KH ^{[1
]}

Huang, CS ^{[1
]}

Lin, CP ^{[1
]}

机构：

[1] Tamkang Univ, Dept Elect Engn, Taipei, Taiwan

来源：

ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In the paper, an efficient VLSI architecture for a 8x 8 two-dimensional discrete cosine transform and inverse discrete cosine transform (2-D DCT/IDCT) with a new 1-D DCT/IDCT algorithm is presented. The proposed new algorithm makes all coefficients are positive to simplify the design of multipliers and the coefficients have less round-off error than Lee's algorithm [1]. For computing 2-D DCT/IDCT. the row-column decomposition method is used, and the design of 1-D DCT/IDCT requires only 9 multipliers and 21 adders/subtractors. This chip is synthesized with 0.6 mu m standard cell library and 1P3M CMOS technology, and it can be operate up to 100MHz.

引用

页码：741 / 744

页数：4

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