An efficient unified framework for implementation of a prime-length DCT/IDCT with high throughput

In this paper, a unified design framework for primelength forward and inverse discrete cosine transforms with a high, throughput is presented. The proposed design facilitates trade-off between the throughput and hardware cost or power consumption, and is well suited for low-power applications. The VLSI structure is highly regular and modular with a topology well suited for the VLSI implementation. The proposed approach is based on the derivation of new efficient systolic algorithms. The algorithms have the same core structure for both the transforms, and the core structure consists of two circular correlations, which unlike other similar computational structures, have the same length and form. Thus, they can be computed in parallel and mapped, on the same linear systolic array with channels having a low I/O bandwidth requirement and their number being independent of the transform length N. Further, it is shown that the two transforms, can be efficiently implemented on the same VLSI chip, where only the pre- and post-processing stages are different. The proposed systolic algorithms retain the benefits provided by VLSI implementations based on circular or cyclic convolution structures, and at the same time has a simpler control structure, high speed and low complexity.