An automated algorithm for partitioning sequential VLSI circuits

This paper presents an automated algorithm that partitions large sequential VLSI circuits for pseudoexhaustive testing. The algorithm utilizes the effect of partitioning on hardware overhead, testing time and the delay of critical path. The pseudoexhaustive testing ensures detection of all detectable faults within individual partitions. We have developed an optimization process that can be used to find the optimal size of primary input cone and fanout values, to be used for partitioning a given circuit. Experimental results are presented to demonstrate the effectiveness of our work. The ISCAS'89 benchmark circuits have been successfully partitioned, and when our results are compared to other partitioning methods, our algorithm makes fewer partitions.