Formal test generation for sequential circuits using global temporal logic

被引：0
|
作者：
He, XH [1 ]
Li, XW [1 ]
机构：
[1] Armored Force Engn Inst, Dept Informat Engn, Beijing 100072, Peoples R China
来源：
CAD/ GRAPHICS TECHNOLOGY AND ITS APPLICATIONS, PROCEEDINGS | 2003年
关键词：
temporal; formal fault; test generation;
D O I：
暂无
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
This paper presents a formal algorithm for unresetable lines circuits using GTL (Global Temporal Logic), which avoids drawbacks of conventional structure approaches. Based on the global temporal logic that defined by forward and reverse operator, a common formal framework for test generation is presented. Some heuristics that accelerate the testing process and its implementation are also given.
引用
收藏
页码：347 / 348
页数：2
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