Design of MOS-translinear multiplier/dividers in analog VLSI

被引：14

作者：

Lopez-Martin, AJ ^{[1
]}

Carlosena, A ^{[1
]}

机构：

[1] Publ Univ Navarra, Dept Elect & Elect Engn, E-31006 Pamplona, Spain

来源：

VLSI DESIGN | 2000年 / 11卷 / 04期

关键词：

analog multiplier/dividers; multipliers; MOS-translinear; voltage-translinear; CMOS analog circuits; analog VLSI;

D O I：

10.1155/2000/21852

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A general framework for designing current-mode CMOS analog multiplier/divider circuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained from a generic second-order MOS translinear loop. Various implementations are proposed, featuring simplicity, favorable precision and wide dynamic range. They can be successfully employed in a wide range of analog VLSI processing tasks. Experimental results of two versions, based on stacked and folded MOS-translinear loops and fabricated in a 2.4-mum CMOS process, are provided in order to verify the correctness of the proposed approach.

引用

页码：321 / 329

页数：9

共 50 条

[41] A design of four-quadrant analog multiplier
Dejhan, K
Prommee, P
Tiamvorratat, W
Mitatha, S
Chaisayun, I
[J]. IEEE INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES 2004 (ISCIT 2004), PROCEEDINGS, VOLS 1 AND 2: SMART INFO-MEDIA SYSTEMS, 2004, : 29 - 32
[42] CMOS-Memristive Analog Multiplier Design
Kalysh, Ileskhan
Krestinskaya, Olga
James, Alex Pappachen
[J]. 2018 2ND INTERNATIONAL CONFERENCE ON COMPUTING AND NETWORK COMMUNICATIONS (COCONET), 2018, : 6 - 10
[43] Bandwidth Extension of Analog Multiplier using Dynamic Threshold MOS Transistor
Chaudhry, Amita
Niranjan, Vandana
Kumar, Ashwni
[J]. 2014 3RD INTERNATIONAL CONFERENCE ON RELIABILITY, INFOCOM TECHNOLOGIES AND OPTIMIZATION (ICRITO) (TRENDS AND FUTURE DIRECTIONS), 2014,
[44] INTEGRATED ANALOG VOLTAGE MULTIPLIER COMBINING MOS AND BIPOLAR-TRANSISTORS
BRATT, AH
KING, D
LYSEJKO, MJ
[J]. ELECTRONICS LETTERS, 1991, 27 (20) : 1853 - 1855
[45] NOVEL ANALOG VLSI DESIGN FOR MULTILAYER NETWORKS
TOMBS, JN
TARASSENKO, L
MURRAY, AF
[J]. IEE PROCEEDINGS-F RADAR AND SIGNAL PROCESSING, 1992, 139 (06) : 426 - 430
[46] Design and implementation of multipattern generators in analog VLSI
Kier, Ryan J.
Ames, Jeffrey C.
Beer, Randall D.
Harrison, Reid R.
[J]. IEEE TRANSACTIONS ON NEURAL NETWORKS, 2006, 17 (04): : 1025 - 1038
[47] Design of high-radix VLSI dividers without quotient selection tables
Aoki, T
Nakazawa, K
Higuchi, T
[J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2001, E84A (11): : 2623 - 2631
[48] VLSI implementation of multiplier design using reversible logic gate
V. Nandhini
K. Sambath
[J]. Analog Integrated Circuits and Signal Processing, 2023, 115 : 93 - 100
[49] VLSI Design of High Speed Vedic Multiplier for FPGA Implementation
Gavali, Kapil Ram
Kadam, Poonam
[J]. PROCEEDINGS OF 2ND IEEE INTERNATIONAL CONFERENCE ON ENGINEERING & TECHNOLOGY ICETECH-2016, 2016, : 936 - 939
[50] VLSI design of a quaternary multiplier with direct generation of partial products
Ishizuka, O
Ohta, A
Tannno, K
Tang, Z
Handoko, D
[J]. 27TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - 1997 PROCEEDINGS, 1997, : 169 - 174

← 1 2 3 4 5 →