A low cost test pattern generator for test-per-clock BIST scheme

被引：0
|
作者：
Lei, Shaochong [1 ]
Wang, Zhen [1 ]
Liu, Zeye [1 ]
Liang, Feng [1 ]
机构：
[1] Xi An Jiao Tong Univ, Sch Elect & Informat, Xian 710049, Peoples R China
来源：
IEICE ELECTRONICS EXPRESS | 2010年 / 7卷 / 10期
关键词：
Built-in self-test; test-per-clock; test pattern generation; single input change; low power;
D O I：
10.1587/elex.7.672
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Test power and test overhead are crucial to VLSI and SOC testing. This paper proposes a low cost test pattern generator (TPG) for test-per-clock built-in self-test (BIST) scheme. The proposed method utilizes a two-dimensional TPG and a bit-XOR array to reduce area overhead, and generates single input change (SIC) sequences to reduce input transitions of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can achieve high fault coverage and effectively reduce test power.
引用
收藏
页码：672 / 677
页数：6
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