An adjacency-based test pattern generator for low power BIST design

A new BIST TPC design that is comprised of an Adjacency-based TPG plus a conventional pseudo-random TPG (i.e. a LFSR) is presented in this paper. When used to generate test patterns for test-per-clock BIST, it reduces the number of transitions that occur in the CUT and hence decreases the average and peak power consumption during resting. Moreover, the total energy consumption during BIST is also reduced since the test length produced by the mixed TPG is roughly the same than the test length produced by a classical LFSR-based TPG to reach the same fault coverage. Note that this TPG design has been developed to deal preferably with strongly connected circuits with a small number of inputs.