A Low Voltage CMOS Analog Multiplier With High Linearity

被引：2
|
作者：
Miremadi, Amir H. [1 ]
Ayatollahi, Ahmad [2 ]
Abrishamifar, Adib [2 ]
Siadatan, Alireza [1 ]
机构：
[1] Islamic Azad Univ, West Tehran Branch, Dept Elect Engn, Tehran, Iran
[2] Iran Univ Sci & Tech, Dept Elect Engn, Tehran, Iran
来源：
2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年
关键词：
4-QUADRANT;
D O I：
10.1109/ECCTD.2009.5274936
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a single low-voltage CMOS analog multiplier with high-linearity, low total harmonic distortion and low-power consumption. It consists of four voltage adders, four nullors and a multiplier core. The proposed circuit is simulated with HSPICE and simulation results have shown that, under single 1V supply voltage, the circuit has smaller than 0.65% linearity error and 0.36% THD under the maximum-scale input 400mVp-p at both inputs. The quiescent power consumption is 120 mu W and the -3dB bandwidth is 30MHz.
引用
收藏
页码：257 / +
页数：2
相关论文
共 50 条
  • [1] Low Voltage, Low Power, High Linearity, High Speed CMOS Voltage Mode Analog Multiplier
    Akshatha, B. C.
    Kumar, A. Vijay
    2009 SECOND INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET 2009), 2009, : 1120 - 1125
  • [2] A low-voltage, low-power, high-linearity CMOS four-quadrant analog multiplier
    Sawigun, Chutham
    Demosthenous, Andreas
    Pal, Dipankar
    2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3, 2007, : 751 - +
  • [3] A low voltage CMOS square law analog multiplier
    Tarim, TB
    Ismail, M
    1999 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, SSMSD 99, 1999, : 5 - 8
  • [4] LOW-VOLTAGE, 4-QUADRANT, ANALOG CMOS MULTIPLIER
    COBAN, AL
    ALLEN, PE
    ELECTRONICS LETTERS, 1994, 30 (13) : 1044 - 1045
  • [5] CMOS voltage-mode analog multiplier
    Boonchu, Boonchai
    Surakampontorn, Wanlop
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 1989 - 1992
  • [6] A low voltage CMOS multiplier for high frequency equalization
    Abbott, J
    Plett, C
    Rogers, JWM
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1936 - 1939
  • [7] Yet another low-voltage four quadrant analog CMOS multiplier
    RamirezAngulo, J
    38TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1996, : 405 - 408
  • [8] Low Voltage High Performance CMOS Current Mode Four-Quadrant Analog Multiplier Circuit
    Ettaghzouti, Thouraya
    Khlaifia, Dalila
    Zitouni, Naoufel
    Hassen, Nejib
    RADIOENGINEERING, 2022, 31 (02) : 216 - 223
  • [9] A low-voltage CMOS linear transconductor suitable for analog multiplier application
    Sawigun, Chutham
    Mahattanakul, Jirayuth
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 1543 - +
  • [10] Low-voltage CMOS analog four quadrant multiplier based on flipped voltage followers
    Ramirez-Angulo, J
    Thoutam, S
    López-Martin, A
    Carvajal, RG
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2004, : 681 - 684
12345