A Low Voltage CMOS Analog Multiplier With High Linearity

被引：2

作者：

Miremadi, Amir H. ^{[1
]}

Ayatollahi, Ahmad ^{[2
]}

Abrishamifar, Adib ^{[2
]}

Siadatan, Alireza ^{[1
]}

机构：

[1] Islamic Azad Univ, West Tehran Branch, Dept Elect Engn, Tehran, Iran

[2] Iran Univ Sci & Tech, Dept Elect Engn, Tehran, Iran

来源：

2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2 | 2009年

关键词：

4-QUADRANT;

D O I：

10.1109/ECCTD.2009.5274936

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a single low-voltage CMOS analog multiplier with high-linearity, low total harmonic distortion and low-power consumption. It consists of four voltage adders, four nullors and a multiplier core. The proposed circuit is simulated with HSPICE and simulation results have shown that, under single 1V supply voltage, the circuit has smaller than 0.65% linearity error and 0.36% THD under the maximum-scale input 400mVp-p at both inputs. The quiescent power consumption is 120 mu W and the -3dB bandwidth is 30MHz.

引用

页码：257 / +

页数：2

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