Booth encoding modulo (2n-2p-1) multipliers

被引：0

作者：

Li, Lei ^{[1
]}

Li, Saiye ^{[1
]}

Yang, Peng ^{[1
]}

Zhang, Qingyu ^{[1
]}

机构：

[1] Univ Elect Sci & Technol China, Res Inst Elect Sci & Technol, Chengdu 611731, Sichuan, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2014年 / 11卷 / 15期

关键词：

residue number systems (RNS); multiplier; 2(N)-1; MULTIPLIERS;

D O I：

10.1587/elex.11.20140588

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this express, we propose Booth encoding high-speed modulo (2(n) - 2(p) - 1) multipliers on the condition length of (Cout) <= min(2(n) - p, n + p), where Cout is the carry-out output of the carry save adder tree that is used to compress the partial products and the correction term after splitting, shifting and resetting. Synthesized results demonstrate that the proposed Booth encoding modulo (2(n) - 2(p) - 1) multipliers have a good delay performance.

引用

页数：6

共 50 条

[1] An universal architecture for designing modulo (2n-2p-1) multipliers
Li, Lei
Hu, Jianhao
Chen, Yiou
IEICE ELECTRONICS EXPRESS, 2012, 9 (03): : 193 - 199
[2] Modified Booth encoding modulo (2n-1) multipliers
Li, Lei
Hu, Jianhao
Chen, Yiou
IEICE ELECTRONICS EXPRESS, 2012, 9 (05): : 352 - 358
[3] Modified Booth modulo 2n-1 multipliers
Efstathiou, C
Vergos, HT
Nikolos, D
IEEE TRANSACTIONS ON COMPUTERS, 2004, 53 (03) : 370 - 374
[4] Multifunction RNS modulo (2n±1) Multipliers Based on Modified Booth Encoding
Juang, Tso-Bing
Huang, Jian-Hao
2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2012, : 515 - 518
[5] Modified Booth 1's complement and modulo 2n-1 multipliers.
Efstathiou, C
Vergos, HT
ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II, 2000, : 637 - 640
[6] An optimized architecture for modulo (2n-2p+1) multipliers
Li, Lei
Yan, Hai
Yang, Peng
Hu, Jianhao
IEICE ELECTRONICS EXPRESS, 2015, 12 (01):
[7] Fast hard multiple generators for radix-8 Booth encoded modulo 2n-1 and modulo 2n+1 multipliers
Muralidharan, Ramya
Chang, Chip-Hong
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 717 - 720
[8] NEW MULTIPLIERS MODULO 2(N)-1
SKAVANTZOS, A
RAO, PB
IEEE TRANSACTIONS ON COMPUTERS, 1992, 41 (08) : 957 - 961
[9] An improved architecture for designing modulo (2n-2p+1) multipliers
Li, Lei
Zhou, Lu
Zhou, Wanting
IEICE ELECTRONICS EXPRESS, 2012, 9 (14): : 1141 - 1146
[10] Novel modulo 2n+1 multipliers
Vergos, H. T.
Efstathiou, C.
DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2006, : 168 - +

← 1 2 3 4 5 →