Booth encoding modulo (2n-2p-1) multipliers

被引：0

作者：

Li, Lei ^{[1
]}

Li, Saiye ^{[1
]}

Yang, Peng ^{[1
]}

Zhang, Qingyu ^{[1
]}

机构：

[1] Univ Elect Sci & Technol China, Res Inst Elect Sci & Technol, Chengdu 611731, Sichuan, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2014年 / 11卷 / 15期

关键词：

residue number systems (RNS); multiplier; 2(N)-1; MULTIPLIERS;

D O I：

10.1587/elex.11.20140588

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this express, we propose Booth encoding high-speed modulo (2(n) - 2(p) - 1) multipliers on the condition length of (Cout) <= min(2(n) - p, n + p), where Cout is the carry-out output of the carry save adder tree that is used to compress the partial products and the correction term after splitting, shifting and resetting. Synthesized results demonstrate that the proposed Booth encoding modulo (2(n) - 2(p) - 1) multipliers have a good delay performance.

引用

页数：6

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