A Coarse-Grained Reconfigurable Architecture for a PRET Machine

Precision Timed (PRET) Machines are architectures designed for use in embedded real-time and cyber-physical systems that provide predictable and repeatable timing properties. Among the characteristics that allow a PRET to achieve such timing properties is the interleaving of hardware threads, present in the majority of the PRET processors developed so far. One of the drawbacks of such thread interleaving is that, in applications that doesn't contain enough Thread-Level Parallelism (TLP), PRET processors suffer from high latencies as 4x or higher when compared to other architectures, and execute many No-Operations. To attack these problems, a Coarse-Grained Reconfigurable Architecture is proposed. Results show that latency and throughput are improved without loosing the desired timing properties of PRET Machines.