A coarse-grained reconfigurable architecture supporting flexible execution

被引：0
|
作者：
Hironaka, T [1 ]
Fukuda, T [1 ]
Goto, Y [1 ]
Tanigawa, K [1 ]
Kawasaki, T [1 ]
Kojima, A [1 ]
机构：
[1] Hiroshima City Univ, Hiroshima, Japan
来源：
SEVENTH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND GRID IN ASIA PACIFIC REGION, PROCEEDINGS | 2004年
关键词：
D O I：
10.1109/HPCASIA.2004.1324073
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
In our research, we have proposed a reconfigurable architecture 'PARS'for general purpose. For developing a software assets required as a general purpose processor the PARS architecture introduces an I-PARS execution model as an ideal execution model for coarse-grained reconfigurable processors. The I-PARS execution model is based on an execution model of an extremely wide VLIW processor With the use of the I-PARS execution model we are not only able to generate the configuration data for step by step execution mode as for the conventional processors, but also possible to generate configuration data for streaming execution mode, which works fine on reconfigurable processors. Further as a processor supporting the above model efficiently, we designed a prototype PARS processor UNITE. In this paper we present the design of the UNITE processor, and show how we support the two execution modes on it. Also we introduce the compiler we are developing for the UNITE processor.
引用
收藏
页码：448 / 449
页数：2
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