Chip Implementation of a Coarse-Grained Reconfigurable Architecture Supporting Floating-Point Operations

被引：0

作者：

Jo, Manhwee ^{[1
]}

Lee, Dongwook ^{[1
]}

Choi, Kiyoung ^{[1
]}

机构：

[1] Seoul Natl Univ, Dept Elect Engn & Comp Sci, Seoul, South Korea

来源：

ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3 | 2008年

关键词：

coarse-grained reconfigurable architecture; floating-point operation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents coarse-grained reconfigurable architecture supporting floating-point operations, where each integer processing element is paired with its neighbor to perform floating point operations. One processing element in a pair is in charge of the mantissa part, and the other is in charge of the exponent part. With an 8x2 array of processing elements, 8 floating-point operations can be performed at the same time. The chip is fabricated in MagnaChip/Hynix 0.18 mu m technology with the gate count of 363,013 and clock frequency of 116.8 MHz in the typical case.

引用

页码：670 / 671

页数：2

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