Block computation architectures for 2-D discrete wavelet transforms

被引：0

作者：

Limqueco, JC ^{[1
]}

Bayoumi, MA ^{[1
]}

机构：

[1] Univ SW Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA

来源：

40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we will introduce two coarse-grained architectures for the block computations of 2-D separable DWT. Parallel-Sequential architecture shows an improvement in computational complexity by a factor of JK, where J is the octave requirement and K is the filter size, when compared to sequential architecture. The parallel-parallel architecture has a computational complexity of O(N), Both architectures are scalable for different filter sizes and octave levels.

引用

页码：865 / 868

页数：4

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