Efficient VLSI architecture for 2-D inverse discrete wavelet transforms

被引：0

作者：

Yu, C ^{[1
]}

Chen, SJ ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 10764, Taiwan

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present a high-performance VLSI architecture for 2-D inverse discrete wavelet transforms (IDWT). The architecture is designed based on a computation-schedule scheme to process the input signals in real-time, and uses two efficient filter structures to minimize the hardware cost. For the computation of an NxN 2-D image with a filter length L, this architecture spends near N-2 clock cycles, and requires about NL storage unit, 3 1/2L, multipliers, as well as 7(L/2 - 1)+4 adders.

引用

页码：524 / 527

页数：4

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