A novel efficient VLSI architecture of 2-D discrete wavelet transform

被引：2

作者：

Hsieh, Chin-Fa ^{[1
]}

Tsai, Tsung-Han ^{[1
]}

Lai, Chih-Hung ^{[1
]}

Shan, Tai-An ^{[1
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Chungli 32054, Taiwan

来源：

2008 FOURTH INTERNATIONAL CONFERENCE ON INTELLIGENT INFORMATION HIDING AND MULTIMEDIA SIGNAL PROCESSING, PROCEEDINGS | 2008年

关键词：

lifting; discrete wavelet transform;

D O I：

10.1109/IIH-MSP.2008.275

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, we propose a novel, efficient VLSI architecture for the implementation of the forward two-dimension, lifting-based discrete wavelet transform (DWT). Replacing the conventional rows and columns alternatively separable method, we extend the 1D-DWT into 2D-DWT directly. The architecture was designed based on the results. The proposed architecture can speed up the computation time to N/2*N/2 for the first level decomposition on an N*N image. The architecture is coded in Verilog HDL and verified by the platform of Quartos-II Finally it is implemented in an Altera Cyclone family FPGA.

引用

页码：647 / 650

页数：4

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