Mathematical foundation on static hazards in multiple-valued logic circuits

被引：0

作者：

Takagi, N ^{[1
]}

Nakashima, K ^{[1
]}

机构：

[1] Toyama Prefectural Univ, Dept Elect & Informat, Fac Engn, Toyama 9390398, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2003年 / E86A卷 / 06期

关键词：

multiple-valued logic; static hazard; prime implicants expression;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The interconnection problem of binary circuits becomes seriously as the exponential growth of the circuits complexity has been driven by a combination of down scaling of the device size and up scaling of the chip size. Motivated by the problem, there is much research of circuits based on multiple-valued logic. On the other hand, caused by the signal propagation delay, there exist hazards in binary logic circuits. To analyze hazards in binary logic circuits, many multiple-valued logics have been proposed, and studied on their mathematical properties. The paper will discuss on a multiple-valued logic which is suitable for treating static hazards in multiple-valued logic circuits. Then, the paper will show that the prime implicants expressions of r-valued logic functions realize static hazards free r-valued logic circuits.

引用

页码：1525 / 1534

页数：10

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