A 0.1-5GHz Dual-VCO Software-Defined ΣΔ Frequency Synthesizer in 45nm Digital CMOS

被引：0
|
作者：
Nuzzo, Pierluigi [1 ]
Vengattaramane, Kameswaran [1 ,2 ]
Ingels, Mark [1 ]
Giannini, Vito [1 ]
Steyaert, Michiel [2 ]
Craninckx, Jan [1 ]
机构：
[1] IMEC, NES Wireless, Kapeldreef 75, B-3001 Louvain, Belgium
[2] Katholieke Univ Leuven, Louvain, Belgium
来源：
RFIC: 2009 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM | 2009年
关键词：
software-defined radio; phase locked loops; voltage controlled oscillators; programmable dividers;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A wide-band frequency synthesizer architecture for software defined radio applications is presented, based on a dual-VCO Sigma Delta phase locked loop (PLL), with a wide-range modulus programmable divider. The design combines high flexibility to cover several wireless standards, with a scalable implementation, exploiting the capabilities of advanced digital technologies at reduced area costs. The prototype in 1.1-V 45-nm digital CMOS achieves a 4.3 to 10GHz PILL tuning range, with programmable K-VCO, bandwidth, between 110 and 320 KHz, and current consumption, ranging from 20 to 29 mA. Measured phase noise is -122dBc/Hz at 2-MHz offset front a 7.2GHz carrier.
引用
收藏
页码：287 / +
页数：2
相关论文
共 50 条
  • [21] Active compensation of supply noise for a 5-GHz VCO in 45-nm CMOS SOI technology
    Nema, Devesh
    Toifl, Thomas
    PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2617 - +
  • [22] A 1GHz Configurable Chirp Modulation Direct Digital Frequency Synthesizer in 65nm CMOS
    Guo, Ting
    Tang, Kai
    Zheng, Yuanjin
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [23] A 0.05-to 10-GHz, 19-to 22-GHz, and 38-to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-μm CMOS Process
    Rong, Sujiang
    Yin, Jun
    Luong, Howard C.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63 (01) : 109 - 113
  • [24] A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS
    Yoo, Taegeun
    Yeoh, Hong Chang
    Jung, Yun-Hwan
    Cho, Seong-Jin
    Kim, Yong Sin
    Kang, Sung-Mo
    Baek, Kwang-Hyun
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (12) : 2976 - 2989
  • [25] A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS
    Borremans, Jonathan
    Vengattaramane, Kameswaran
    Giannini, Vito
    Debaillie, Bjoern
    Van Thillo, Wim
    Craninckx, Jan
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (10) : 2116 - 2129
  • [26] A 5 mm2 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform
    Ingels, Mark
    Giannini, Vito
    Borremans, Jonathan
    Mandal, Gunjan
    Debaillie, Bjorn
    Van Wesemael, Peter
    Sano, Tomohiro
    Yamamoto, Takaya
    Hauspie, Dries
    Van Driessche, Joris
    Craninckx, Jan
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (12) : 2794 - 2806
  • [27] A compact 0.045-2.3GHz frequency synthesizer with a wide tuning range low phase noise VCO for software defined radios
    Hu, Ang
    Liu, Dongsheng
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2019, 100 (01) : 1 - 10
  • [28] An integrated 0.0625-4 GHz quadrature-output fractional-N frequency synthesizer for software-defined radios
    Yao, Yan
    Li, Zhiqun
    Li, Zhennan
    Chen, Bofan
    Wang, Xiaowei
    MICROELECTRONICS JOURNAL, 2022, 119
  • [29] A Two-Stage LNA Design for 28GHz Band Of 5G on 45nm CMOS
    Jarvenhaara, J.
    Filanovsky, I. M.
    Nevalainen, I
    Tchamov, N. T.
    2020 IEEE 63RD INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2020, : 957 - 961
  • [30] A 2GHz Digital PLL, with Temperature Lock Range of-40°C to 125°C, in 45nm CMOS
    Chattopadhyay, Biman
    Kamath, Anant S.
    Evani, Satyasai
    Subburaj, Karthik
    2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2011,
12345