A 0.1-5GHz Dual-VCO Software-Defined ΣΔ Frequency Synthesizer in 45nm Digital CMOS

被引：0

作者：

Nuzzo, Pierluigi ^{[1
]}

Vengattaramane, Kameswaran ^{[1
,2
]}

Ingels, Mark ^{[1
]}

Giannini, Vito ^{[1
]}

Steyaert, Michiel ^{[2
]}

Craninckx, Jan ^{[1
]}

机构：

[1] IMEC, NES Wireless, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, Louvain, Belgium

来源：

RFIC: 2009 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM | 2009年

关键词：

software-defined radio; phase locked loops; voltage controlled oscillators; programmable dividers;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A wide-band frequency synthesizer architecture for software defined radio applications is presented, based on a dual-VCO Sigma Delta phase locked loop (PLL), with a wide-range modulus programmable divider. The design combines high flexibility to cover several wireless standards, with a scalable implementation, exploiting the capabilities of advanced digital technologies at reduced area costs. The prototype in 1.1-V 45-nm digital CMOS achieves a 4.3 to 10GHz PILL tuning range, with programmable K-VCO, bandwidth, between 110 and 320 KHz, and current consumption, ranging from 20 to 29 mA. Measured phase noise is -122dBc/Hz at 2-MHz offset front a 7.2GHz carrier.

引用

页码：287 / +

页数：2

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