A 0.1-5GHz Dual-VCO Software-Defined ΣΔ Frequency Synthesizer in 45nm Digital CMOS

被引：0

作者：

Nuzzo, Pierluigi ^{[1
]}

Vengattaramane, Kameswaran ^{[1
,2
]}

Ingels, Mark ^{[1
]}

Giannini, Vito ^{[1
]}

Steyaert, Michiel ^{[2
]}

Craninckx, Jan ^{[1
]}

机构：

[1] IMEC, NES Wireless, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, Louvain, Belgium

来源：

RFIC: 2009 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM | 2009年

关键词：

software-defined radio; phase locked loops; voltage controlled oscillators; programmable dividers;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A wide-band frequency synthesizer architecture for software defined radio applications is presented, based on a dual-VCO Sigma Delta phase locked loop (PLL), with a wide-range modulus programmable divider. The design combines high flexibility to cover several wireless standards, with a scalable implementation, exploiting the capabilities of advanced digital technologies at reduced area costs. The prototype in 1.1-V 45-nm digital CMOS achieves a 4.3 to 10GHz PILL tuning range, with programmable K-VCO, bandwidth, between 110 and 320 KHz, and current consumption, ranging from 20 to 29 mA. Measured phase noise is -122dBc/Hz at 2-MHz offset front a 7.2GHz carrier.

引用

页码：287 / +

页数：2

共 50 条

[31] A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO
曹圣国
杨玉庆
谈熙
闫娜
闵昊
Journal of Semiconductors, 2011, 32 (08) : 98 - 103
[32] A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO
Cao Shengguo
Yang Yuqing
Tan Xi
Yan Na
Min Hao
JOURNAL OF SEMICONDUCTORS, 2011, 32 (08)
[33] A 1.3GHz 350mW Hybrid Direct Digital Frequency Synthesizer in 90nm CMOS
Yeoh, Hong Chang
Jung, Jae-Hun
Jung, Yun-Hwan
Baek, Kwang-Hyun
2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2009, : 122 - 123
[34] A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS
Yeoh, Hong Chang
Jung, Jae-Hun
Jung, Yun-Hwan
Baek, Kwang-Hyun
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (09) : 1845 - 1855
[35] A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology
Yang, Song-Yu
Chen, Wei-Zen
Lu, Tai-You
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (03) : 578 - 586
[36] A 130-nm CMOS 100-Hz-6-GHz Reconfigurable Vector Signal Analyzer and Software-Defined Receiver
Goel, Ankush
Analui, Behnam
Hashemi, Hossein
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2012, 60 (05) : 1375 - 1389
[37] 36% Frequency-Tuning-Range Dual-Core 60 GHz Push-Push VCO in 45 nm RF-SOI CMOS Technology
Rimmelspacher, Johannes
Weigel, Robert
Hagelauer, Amelie
Issakov, Vadim
2017 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS), 2017, : 1352 - 1354
[38] A 23.67-to-45-GHz Wide Tuning Range Dual VCO with Phase Noise Enhancement in 90-nm CMOS Technology
Li, Wei-Tsung
Cheng, Jen-Hao
Wu, Yi-Ming
Huang, Tian-Wei
2013 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST (IMS), 2013,
[39] Lock Detector Integrated in a High Order Frequency Multiplier Operating at 60-GHz-Band in 45nm CMOS SOI Technology
Boulmirat, Abdessamad
Siligaris, Alexandre
Jany, Clement
Gonzalez-Jimenez, Jose L.
PROCEEDINGS OF THE 2020 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS), 2020, : 944 - 947
[40] A 180-nm CMOS 100MHz-1.2GHz Software-Defined Transceiver with Integrated Pre-Power Amplifier
Fu, Haipeng
Li, Xuguang
Ma, Kaixue
Wu, Haifeng
2019 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT2019), 2019,

← 1 2 3 4 5 →