Less Reliable Page Error Reduction for 3D-TLC NAND Flash Memories with Data Overhead Reduction by 40% and Data-retention Time Increase by 5.0x

被引：0
|
作者：
Maeda, Kyosuke [1 ]
Mizoguchi, Kyoji [1 ]
Takeuchi, Ken [1 ]
机构：
[1] Chuo Univ, Dept Elect Elect & Commun Engn, Tokyo, Japan
来源：
2019 SILICON NANOELECTRONICS WORKSHOP (SNW) | 2019年
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D O I：
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes Less Reliable Page Error Reduction (LRPER) to achieve both high reliability and small data overhead of 3D-TLC NAND flash memories. LRPER suppresses both lateral charge migration and vertical charge de-trap without redundant reading of memory cells, thus achieving fast write. In addition, data overhead is small by adding flag bits to the highly reliable page. As a result, the data-retention lifetime increases by 5.0-times. The proposal can be implemented in the SSD controller for highly reliable 3D-NAND flash.
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页码：31 / 32
页数：2
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