Pre-shipment Data-retention/Read-disturb Lifetime Prediction & Aftermarket Cell Error Detection & Correction by Neural Network for 3D-TLC NAND Flash Memory

被引：0
|
作者：
Abe, Masaki [1 ]
Nakamura, Toshiki [1 ]
Takeuchi, Ken [1 ]
机构：
[1] Chuo Univ, Bunkyo Ku, 1-13-27 Kasuga, Tokyo 1128551, Japan
来源：
2019 SYMPOSIUM ON VLSI TECHNOLOGY | 2019年
关键词：
D O I：
10.23919/vlsit.2019.8776480
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper proposes 2 neural network (NN) techniques for 3D-TLC (Triple-Level Cell) NAND flash memory. 1) Predict data-retention/read-disturb lifetime for chip sorting during preshipment test. 2) Detect and correct errors in aftermarket. First, in pre-shipment test, Neural Network-based Lifetime Prediction (NNLP) predicts ECC decoding fail rate (EDFR) and estimates data-retention/read-disturb lifetime. Based on predicted lifetime, NNLP sorts NAND flash. Second, in aftermarket, Neural Network-based Error Detection (NNED) detects and corrects errors. NNED decreases bit-error rate (BER) by 81.4%.
引用
收藏
页码：T216 / T217
页数：2
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