12x Bit-Error Acceptable, 300x Extended Data-Retention Time, Value-Aware SSD with Vertical 3D-TLC NAND Flash Memories for Image Recognition

被引：0
|
作者：
Deguchi, Yoshiaki [1 ]
Nakamura, Toshiki [1 ]
Kobayashi, Atsuro [1 ]
Takeuchi, Ken [1 ]
机构：
[1] Chuo Univ, Dept Elect Elect & Commun Engn, Tokyo, Japan
来源：
2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2017年
关键词：
vertical NAND flash memory; ECC; SSD; Image recognition;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Value-Aware SSD with Vertical 3D-TLC (Triple-Level Cell) NAND flash for the image recognition is proposed to increase the acceptable bit-error rate (BER) by 12-times and extend the data-retention time by 300 times. In addition to the reliability improvement, the read time reduces by 26%. The proposed SSD combines new data-aware techniques with deep neural network's error tolerance. 10% BER of NAND flash is allowed while providing the accurate and fast image recognition. The design overhead in the SSD controller is negligibly small.
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页数：4
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