Error Elimination ECC by Horizontal Error Detection and Vertical-LDPC ECC to Increase Data-Retention Time by 230% and Acceptable Bit-Error Rate by 90% for 3D-NAND Flash SSDs

被引：0

作者：

Suzuki, Shun ^{[1
]}

Deguchi, Yoshiaki ^{[1
]}

Nakamura, Toshiki ^{[1
]}

Mizoguchi, Kyoji ^{[1
]}

Takeuchi, Ken ^{[1
]}

机构：

[1] Chuo Univ, Dept Elect Elect & Commun Engn, Tokyo, Japan

来源：

2018 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2018年

关键词：

3D-TLC NAND flash; error detection; LDPC; SSD; 2D;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Cross Error Elimination (XEE) ECC with Horizontal Error Detection (HED) and Vertical-LDPC (V-LDPC) is proposed to extend the data-retention lifetime of 3D-TLC NAND flash-based SSD. HED improves the error correction capability of LDPC ECC by evaluating the error bits in the horizontal direction which means the column direction. Moreover, V-LDPC improves the worst reliability in each WL in the vertical row direction through three (Upper/Middle/Lower) pages. This paper investigates the reliability improvement of 3D-TLC NAND flash memory by XEE ECC. As a result, the data-retention lifetime and the acceptable bit-error rate (BER) are extended by 230% and 90%, respectively.

引用

页数：4

共 5 条

[1] 12x Bit-Error Acceptable, 300x Extended Data-Retention Time, Value-Aware SSD with Vertical 3D-TLC NAND Flash Memories for Image Recognition
Deguchi, Yoshiaki
Nakamura, Toshiki
Kobayashi, Atsuro
Takeuchi, Ken
[J]. 2017 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2017,
[2] 9.1x Error Acceptable Adaptive Artificial Neural Network Coupled LDPC ECC for Charge-trap and Floating-gate 3D-NAND Flash Memories
Nakamura, Toshiki
Deguchi, Yoshiaki
Takeuchi, Ken
[J]. 2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2018,
[3] Less Reliable Page Error Reduction for 3D-TLC NAND Flash Memories with Data Overhead Reduction by 40% and Data-retention Time Increase by 5.0x
Maeda, Kyosuke
Mizoguchi, Kyoji
Takeuchi, Ken
[J]. 2019 SILICON NANOELECTRONICS WORKSHOP (SNW), 2019, : 31 - 32
[4] Error Crrection for Read-hot Data in 3D-TLC NAND Flash by Read-disturb Modeled Artificial Neural Network Coupled LDPC ECC
Kojima, Daiki
Nakamura, Toshiki
Takeuchi, Ken
[J]. 2019 SILICON NANOELECTRONICS WORKSHOP (SNW), 2019, : 29 - 30
[5] Pre-shipment Data-retention/Read-disturb Lifetime Prediction & Aftermarket Cell Error Detection & Correction by Neural Network for 3D-TLC NAND Flash Memory
Abe, Masaki
Nakamura, Toshiki
Takeuchi, Ken
[J]. 2019 SYMPOSIUM ON VLSI TECHNOLOGY, 2019, : T216 - T217

← 1 →