Data Pattern & Memory Variation Aware Fine-Grained ECC Optimized by Neural Network for 3D-TLC NAND Flash Memories with 2.0x Data-retention Time Extension and 30% Parity Overhead Reduction

被引:3
|
作者
Nakamura, Toshiki [1 ]
Suzuki, Shun [1 ]
Takeuchi, Ken [1 ]
机构
[1] Chuo Univ, Dept Elect Elect & Commun Engn, Tokyo, Japan
关键词
3D-TLC NAND flash memory; ECC; neural network; automatic design;
D O I
10.1109/imw.2019.8739730
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes fine-grained ECC optimized by Neural Network ( NN) for 3D-TLC NAND flash memories. Among 48 combinations of 8 reliability enhancement techniques ( RETs) and 6 BCH ECCs, proposed NN automatically selects the optimal combination of RET and BCH ECC. Errors with complicated data pattern dependence and memory variations are adaptively compensated. In addition, the design trade-off between the high reliability and parity overhead ( cost) is resolved. As a result, both high reliability and small parity overhead are realized simultaneously. The acceptable data-retention time increases by 2.0-times and the data overhead decreases by 30%.
引用
收藏
页码:144 / 147
页数:4
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