This study analyzes the influence of the interval of time (tS-P) between write/erase endurance stress and programming the final data for the data-retention and read-disturb error evaluations in 1X nm triple-level cell (TLC) NAND flash memories. During the interval of time after the write/erase endurance stresses, electrons are de-trapped from the tunnel dielectric. Eventually, the data-retention error decreases in read-"cold" data which is infrequently read. By introducing long tS-P, e.g., 3 h, with round-robin wear-leveling, the bit error rate (BER) of the read-cold data can be decreased by 47%. Moreover, in read-"hot" data which is frequently read, the BER decreases because VTH-down errors are decreased by introducing long tS-P in over 600 read cycles, while the BER does not decrease in case of the smaller read cycles (< 600) because VTH-up errors increase during the read operations. This work introduces the mechanism of the VTH-down error in read-"hot" data. The measured BER of the read-hot data decreases by 74% by introducing optimal tS-P with round-robin wear-leveling. (c) 2017 The Japan Society of Applied Physics
