Energy-Efficient FinFET- Versus TFET-Based STT-MRAM Bitcells

被引：2

作者：

Musello, Ariana ^{[1
]}

Perez, Santiago S. ^{[1
]}

Villegas, Marco ^{[1
]}

Procel, Luis Miguel ^{[1
]}

Taco, Ramiro ^{[1
]}

Trojman, Lionel ^{[1
,2
]}

机构：

[1] Univ San Francisco Quito USFQ, Inst Micro & Nanoelect IMNE, Quito 170901, Ecuador

[2] Inst Super Elect Paris ISEP, 10 Rue Vanves, F-92130 Issy Les Moulineaux, France

来源：

2022 IEEE 13TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS) | 2022年

关键词：

STT-MRAM; double-barrier magnetic tunnel junction (DMTJ); tunnel FET (TFET); FinFET; ultralow voltage;

D O I：

10.1109/LASCAS53948.2022.9789086

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuit-level, benchmarking TFET-against FinFET-based bitcells focusing on their write operation. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies in a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.

引用

页码：29 / 32

页数：4

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