High-Density STT-Assisted SOT-MRAM (SAS-MRAM) for Energy-Efficient AI Applications

被引:0
|
作者
Xue, Fen [1 ]
Hwang, William [1 ]
Zhang, Fan [2 ]
Tsai, Wilman [3 ]
Fan, Deliang [2 ]
Wang, Shan X. [1 ,3 ]
机构
[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94350 USA
[2] Johns Hopkins Univ, Dept Elect & Comp Engn, Baltimore, MD 21218 USA
[3] Stanford Univ, Dept Mat Sci & Engn, Stanford, CA 94305 USA
关键词
Artificial intelligence (AI) hardware; energy-efficient computing; SAS-MRAM; spin-orbit torque (SOT); spintronics; spin-transfer torque (STT); MAGNETIC TUNNEL-JUNCTION; SPIN-ORBIT; TORQUE MEMORY;
D O I
10.1109/TMAG.2024.3486616
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Energy-efficient computing is essential for addressing the rising power demands of modern data-intensive applications and ensuring sustainable technology advancement. Magnetoresistive random access memory (MRAM) has emerged as a pivotal technology in this domain, offering nonvolatile memory solutions that combine low power consumption with high performance. Spin-orbit torque (SOT) MRAM (SOT-MRAM) and its variants stand out for its potential to deliver SRAM-like performance at a higher bit-cell density. In this article, we present a novel high-density STT-assisted SOT-MRAM (SAS-MRAM) technology designed for energy-efficient artificial intelligence (AI) applications. SAS-MRAM capitalizes on the advantages of both spin-transfer torque (STT) and SOT mechanisms, utilizing a multi-bit-shared SOT line to achieve high-speed, high-density, and high-endurance memory performance. Our experimental results validate the potential of SAS-MRAM to address the limitations of current memory technologies. An AI application of ResNet-18 deployed in SAS-MRAM shows similar to 32.7x energy-delay-product (EDP) benefits compared to that in SRAM, presenting a promising solution for future AI hardware implementations, especially at edge where low-power training and inference of AI models are necessary.
引用
收藏
页数:8
相关论文
共 50 条
  • [1] Energy Efficient Computing With High-Density, Field-Free STT-Assisted SOT-MRAM (SAS-MRAM)
    Hwang, William
    Xue, Fen
    Zhang, Fan
    Song, Ming-Yuan
    Lee, Chien-Min
    Turgut, Emrah
    Chen, T. C.
    Bao, Xinyu
    Tsai, Wilman
    Fan, Deliang
    Wang, Shan X.
    IEEE TRANSACTIONS ON MAGNETICS, 2023, 59 (03)
  • [2] Experimental Demonstration of Field-Free STT-Assisted SOT-MRAM (SAS-MRAM) With Four Bits per SOT Programming Line
    Hwang, William
    Xue, Fen
    Song, Ming-Yuan
    Hsu, Chen-Feng
    Chen, T. C.
    Tsai, Wilman
    Bao, Xinyu
    Wang, Shan X.
    IEEE ELECTRON DEVICE LETTERS, 2024, 45 (10) : 1800 - 1803
  • [3] High-Density SOT-MRAM Based on Shared Bitline Structure
    Seo, Yeongkyo
    Roy, Kaushik
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (08) : 1600 - 1603
  • [4] Multilevel SOT-MRAM Cell with a Novel Sensing Scheme for High-Density Memory Applications
    Zeinali, Behzad
    Esmaeili, Mahsa
    Madsen, Jens K.
    Moradi, Farshad
    2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2017, : 172 - 175
  • [5] High Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM
    He, Zhezhi
    Angizi, Shaahin
    Parveen, Farhana
    Fan, Deliang
    PROCEEDINGS OF THE IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH 2017), 2017, : 97 - 102
  • [6] A STT-Assisted SOT MRAM-Based In-Memory Booth Multiplier for Neural Network Applications
    Wu, Jiayao
    Wang, Yijiao
    Wang, Pengxu
    Wang, Yiming
    Zhao, Weisheng
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2024, 23 : 29 - 34
  • [7] A STT-Assisted SOT MRAM-Based In-Memory Booth Multiplier for Neural Network Applications
    Wu, Jiayao
    Wang, Yijiao
    Wang, Pengxu
    Wang, Yiming
    Zhao, Weisheng
    IEEE Transactions on Nanotechnology, 2024, 23 : 29 - 34
  • [8] SOT and STT Based Four-Bit Parallel MRAM Cell for High-Density Applications
    Dhull, Seema
    Nisar, Arshid
    Kaushik, Brajesh Kumar
    IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2021, 20 : 653 - 661
  • [9] Design Space Exploration of a 512KB STT-Assisted SOT MRAM Cache
    Caburnay, Adrian G.
    Reyes, Jonathan Gabriel S. A.
    Ballesil-Alvarez, Anastacia P.
    de Leon, Maria Theresa G.
    Hizon, John Richard E.
    Rosales, Marc D.
    Santos, Christopher G.
    Sabino, Maria Patricia Rouelli G.
    2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020), 2020, : 145 - 146
  • [10] Write-Efficient STT/SOT Hybrid Triple-Level Cell for High-Density MRAM
    Xu, Yansong
    Wu, Bi
    Wang, Zhaohao
    Wang, Yijiao
    Zhang, Youguang
    Zhao, Weisheng
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (04) : 1460 - 1465