A generic reconfigurable neural network architecture implemented as a network on chip

被引：19
|
作者：
Theocharides, T [1 ]
Link, G [1 ]
Vijaykrishnan, N [1 ]
Irwin, MJ [1 ]
Srikantam, V [1 ]
机构：
[1] Penn State Univ, University Pk, PA 16802 USA
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2004年
关键词：
D O I：
10.1109/SOCC.2004.1362404
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Neural networks are widely used in pattern recognition, security applications and data manipulation. We propose a novel hardware architecture for a generic neural network, using Network on Chip (NoC) interconnect. The proposed architecture allows for expandability, mapping of more than one logical unit onto a single physical unit, and dynamic reconfiguration based on application-specific demands. Simulation results show that this architecture has significant performance benefits over existing architectures.
引用
收藏
页码：191 / 194
页数：4
相关论文
共 50 条
  • [1] NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture
    Liu, Yuhao
    Rai, Shubham
    Ullah, Salim
    Kumar, Akash
    [J]. 2022 21ST INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (ICFPT 2022), 2022, : 323 - 323
  • [2] A generic network-on-chip architecture for reconfigurable systems:: Implementation and evaluation
    Vestias, Mario P.
    Neto, Horacio C.
    [J]. 2006 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, 2006, : 737 - 740
  • [3] An Efficient Reconfigurable Neural Network on Chip
    Khalil, Kasem
    Dey, Bappaditya
    Abdelrehim, Mostafa
    Kumar, Ashok
    Bayoumi, Magdy
    [J]. 2021 28TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (IEEE ICECS 2021), 2021,
  • [4] Network on Chip architecture for BP Neural Network
    Yiping Dong
    Takahiro, Watanabe
    [J]. 2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEM, 2008, : 1083 - 1087
  • [5] NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs
    Liu, Yuhao
    Rai, Shubham
    Ullah, Salim
    Kumar, Akash
    [J]. 2023 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS, IPDPSW, 2023, : 85 - 92
  • [6] Reconfigurable Network-on-Chip Security Architecture
    Charles, Subodha
    Mishra, Prabhat
    [J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2020, 25 (06)
  • [7] ReNoC: A network-on-chip architecture with reconfigurable topology
    Stensgaard, Mikkel B.
    Sparso, Jens
    [J]. NOCS 2008: SECOND IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, PROCEEDINGS, 2007, : 55 - 64
  • [8] When reconfigurable architecture meets network-on-chip
    Soares, R
    Silva, IS
    Azevedo, A
    [J]. SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, 2004, : 216 - 221
  • [9] An Efficient Dynamically Reconfigurable On-chip Network Architecture
    Modarressi, Mehdi
    Sarbazi-Azad, Hamid
    Tavakkol, Arash
    [J]. PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 166 - 169
  • [10] Reconfigurable Network-on-Chip based Convolutional Neural Network Accelerator
    Firuzan, Arash
    Modarressi, Mehdi
    Reshadi, Midia
    [J]. JOURNAL OF SYSTEMS ARCHITECTURE, 2022, 129
12345